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<div class="header">
  <div class="headertitle"><div class="title">SPDIFRX_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>SPDIF-RX Interface.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:af97c3ae3a1ced6864b75ee530d96e2d7" id="r_af97c3ae3a1ced6864b75ee530d96e2d7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af97c3ae3a1ced6864b75ee530d96e2d7">CR</a></td></tr>
<tr class="memitem:a215b72b46132acd63634cd950c1f81c4" id="r_a215b72b46132acd63634cd950c1f81c4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a215b72b46132acd63634cd950c1f81c4">IMR</a></td></tr>
<tr class="memitem:ad3ff338b3b53a2d26d0154b0037e2a20" id="r_ad3ff338b3b53a2d26d0154b0037e2a20"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad3ff338b3b53a2d26d0154b0037e2a20">SR</a></td></tr>
<tr class="memitem:a380aef459d7c44683aae4cd6e9710a7d" id="r_a380aef459d7c44683aae4cd6e9710a7d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a380aef459d7c44683aae4cd6e9710a7d">IFCR</a></td></tr>
<tr class="memitem:aaffe413c3f6f3153b8b0b953df96e924" id="r_aaffe413c3f6f3153b8b0b953df96e924"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aaffe413c3f6f3153b8b0b953df96e924">DR</a></td></tr>
<tr class="memitem:a8d811e4f5a16f36d6cb45d1369eec51b" id="r_a8d811e4f5a16f36d6cb45d1369eec51b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8d811e4f5a16f36d6cb45d1369eec51b">CSR</a></td></tr>
<tr class="memitem:a76f50bd37d940fd507da3fec5326c96a" id="r_a76f50bd37d940fd507da3fec5326c96a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a76f50bd37d940fd507da3fec5326c96a">DIR</a></td></tr>
<tr class="memitem:a50425a2dba4883cf40f1f16805daa8e9" id="r_a50425a2dba4883cf40f1f16805daa8e9"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a50425a2dba4883cf40f1f16805daa8e9">RESERVED2</a></td></tr>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>SPDIF-RX Interface. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#af97c3ae3a1ced6864b75ee530d96e2d7">&#9670;&#160;</a></span>CR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPDIFRX_TypeDef::CR</td>
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<p>Control register, Address offset: 0x00 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8d811e4f5a16f36d6cb45d1369eec51b">&#9670;&#160;</a></span>CSR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPDIFRX_TypeDef::CSR</td>
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<p>Channel Status register, Address offset: 0x14 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a76f50bd37d940fd507da3fec5326c96a">&#9670;&#160;</a></span>DIR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPDIFRX_TypeDef::DIR</td>
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<p>Debug Information register, Address offset: 0x18 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aaffe413c3f6f3153b8b0b953df96e924">&#9670;&#160;</a></span>DR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPDIFRX_TypeDef::DR</td>
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<p>Data input register, Address offset: 0x10 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a380aef459d7c44683aae4cd6e9710a7d">&#9670;&#160;</a></span>IFCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPDIFRX_TypeDef::IFCR</td>
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<p>Interrupt Flag Clear register, Address offset: 0x0C </p>

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<a id="a215b72b46132acd63634cd950c1f81c4" name="a215b72b46132acd63634cd950c1f81c4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a215b72b46132acd63634cd950c1f81c4">&#9670;&#160;</a></span>IMR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPDIFRX_TypeDef::IMR</td>
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<p>Interrupt mask register, Address offset: 0x04 </p>

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          <td class="memname">uint32_t SPDIFRX_TypeDef::RESERVED2</td>
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<p>Reserved, 0x1A </p>

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<a id="ad3ff338b3b53a2d26d0154b0037e2a20" name="ad3ff338b3b53a2d26d0154b0037e2a20"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad3ff338b3b53a2d26d0154b0037e2a20">&#9670;&#160;</a></span>SR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SPDIFRX_TypeDef::SR</td>
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<p>Status register, Address offset: 0x08 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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